1. Field of the Invention
The invention relates generally to semiconductor devices and related methods of manufacture. More particularly, the invention relates to a field effect transistor and method for manufacturing the same.
A claim of priority is made to Korean Patent application 2004-18428 filed Mar. 18, 2004, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
Contemporary semiconductor devices are characterized in one regard by high integration densities. Accordingly, various methods have been proposed to reduce the physical feature size of individual devices formed on a constituent semiconductor substrate while at the same time maintaining the functional performance characteristics of the devices. Some of these conventional methods have been applied to the formation of field effect transistors (FETs) which are common devices apparent in Complementary Metal Oxide Semiconductor (CMOS) circuits and devices.
Unfortunately, continued reduction in the size of FETs poses some real problems. For example, the formation of a planar structure FET on a contemporary single-crystal silicon substrate with a gate electrode having a length less than 500 Å is particularly sensitive to variations in process conditions. Accordingly, it is difficult to control the performance characteristics of the resulting FET. As a result, various conventional attempts have been made to control the performance of FETs. U.S. Pat. No. 5,675,164, for example, proposes increasing a channel width of the gate electrode instead of a channel length in order to stabilize FET performance over variations in process conditions.
FIGS. 1a and 1b are related plan and sectional views illustrating the structure of a conventional FET. In the conventional FET, an active region “AA” under a gate electrode has a structure comprising numerous mesa-like structures (hereafter “mesas”) 11, each having a width of under a micron. This arrangement has the effect of increasing the effective channel width of the device.
A manufacturing method adapted to produce this conventional FET structure will now be described.
First, a silicon oxide layer having a predetermined thickness is formed on a semiconductor substrate. A photoresist is then deposited on the silicon oxide layer and patterned using a photolithography process and a related mask having a desired line pattern with a sub micron pitch.
Subsequently, the silicon oxide layer is selectively removed by using the photoresist as an etch mask.
Next, the semiconductor substrate is etched to a predetermined depth using the silicon oxide layer as an etch mask, such that grooves are selectively formed to yield the mesas 11. Groove depth is determined in proportion to the pattern pitch of the silicon oxide layer and in relation to a desired width for the mesas. The groove forming the mesas is formed with a high aspect ratio defined by the vertical intersection of the groove's sidewall with the bottom face of the groove. However, in cases where the intersection of the sidewall and bottom is formed at a negative angle smaller than 90°, performance of the FET is diminished. Accordingly, a silicon oxide layer of predetermined thickness is generally formed on the bottom face of groove using, for example, a liquid phase deposition to remedy this potential problem.
Following this remedial step, a gate insulation layer (not shown) of predetermined thickness is formed on an active region of the resulting structure including the mesas.
A gate electrode and an upper gate insulation layer are then formed on a gate region of the active region on which the gate insulation layer was formed. A low density of impurity having a predetermined conductivity type is ion implanted in the source (S) and drain (D) regions using the gate electrode as an ion implantation mask, thereby forming a first impurity region.
A spacer is then formed on a sidewall of the gate electrode, and a high density of impurity is ion implanted in the source/drain regions by using the spacer and gate upper insulation layer as an ion implantation mask, thereby forming a second impurity region. Then, a pad polysilicon layer is formed on the second impurity region.
The foregoing conventional FET manufacturing method can increase the effective channel width by means of grooves forming multiple mesas in the gate region. However, the conventional FET and related manufacturing method are not without distinct disadvantages.
For example, as noted above with respect to the conventional FET manufacturing method, mesas 11 and the gate electrode are formed from polysilicon. It is difficult to accurately reproduce in polysilicon the desired corner flute of the mesas. Namely the desired right-angle intersection between the sidewall and bottom of the groove is difficult to achieve. Rather, a negative angle is often produced and performance of the FET suffers accordingly.
Additionally, it is difficult to accurately and reproducibly remove portions of the polysilicon layer so as to form the corner flute of the mesas formed on a source/drain region, such that the polysilicon layer forming the gate electrode is impaired and reliability of the FET suffers.
Additionally, as noted above, the additional formation of a silicon oxide layer over the bottom faces of the groove forming the mesas is required in order to prevent polysilicon layer defects generated in the corner flutes of the mesa structure from adversely defining the angle of intersection between the sidewall and bottom face of the grove. As a result, the bottom face of the groove cannot be used as a channel, thus lowering performance of the FET.